summarized these steps, which will guide you during PCB Layout process. Let me know when you find them useful
First Phase – Connecting all the pins
A: Set up basic rules
For example [mm]: Track 0.1 / 0.1 (clearance / width) , VIA 0.45/0.2 (diameter / drill), DIFF pair 0.1/0.1/0.1 (track / gap / track)
B: Set up a basic stackup
Add more layers and you will remove unused layers on the end.
C: Do preliminary memory layout
D: Do CPU fanouts
By priority (first with highest priority): Powers, Decoupling capacitors, Precise resistors / capacitors, Crystals, Series resistors / capacitors,
Termination resistors, Pull UP / DOWN resistors, Bootstrap resistors.
E: Do fanout for other difficult BGAs in design (e.g. FPGA, chipset, …)
F: Route big and wide buses (e.g. PCI, ISA, …)
Do all the fanouts in the way of the bus, so you don’t have to reroute it later.
G: Do preliminary differential pair routing
H: Connect Long Length Buses, then rest of High pin number buses
I: Do local connections
These are usually connections in small area e.g. Power supply components, Small circuits, Connectors, Analog areas
J: Connect rest of the still unconnected signals (e.g. 1 wire nets, LEDs, …)
K: (or Step 0) Connect power nets
Design power planes. If your design is difficult, or number of power layers is very limited, you may want to do preliminary power distribution on very
beginning of layout.
L: Clear DRCs
Second Phase – Improving your Layout
A: Set the real stackup
Use the information provided by your PCB manufacturer or design your own.
B: Set the real differential pair rules based on stackup
Use the track geometry provided by your PCB manufacturer
C: Do preliminary memory interface length matching
The signals don’t have to be nice at this stage, the goal is occupy the space needed to length match the signals.
D: Do preliminary differential pair length matching
Reroute differential pairs with the new track geometry defined by target impedance & stackup, occupy the space needed to length match the signals later.
E: Add stitching VIAs
Find more information for example here (page 11).
F: Do preliminary length matching of other signals (e.g. clocks, …)
G: Check high current tracks
Add / modify polygons were needed. Calculate track width and VIA number.
H: Check power planes
Go from the source, be sure there is enough vias and copper for the current.
I: Check all the nets one-by-one
Go through all the nets in your board. Double check for example wider space around clock signals, interrupts, …
J: Do final length matching of simple signals & differential pairs
K: Do final length matching of memory interface
L: Lock down important tracks (e.g. memory interface tracks)
M: Add: Company name, Copyright, Year, Board name & Version, …
N: Add manufacturing information (e.g. PCB color, Tolerances, …)